Hi, I noticed the following warning in the Opto JIT Code for the Vector API in the test/jdk/jdk/incubator/vector/Byte256VectorTests.java:ASHRByte256VectorTests test:
```
--------------------------------------------------------------------------------
** Rejected vector op (RShiftVB,byte,32) because architecture does not support variable vector shifts
** not supported: arity=2 opc=405 vlen=32 etype=byte ismask=0 is_masked_op=0
```
the reason is because Matcher::supports_vector_ variable_shifts returns false. riscv vector api now supports the vector shifts, so this should return with UseRVV.
After the fix, the test passes normally and generates the JIT Code such as:
```
1c2 loadV V1, [R7] # vector (rvv)
1ca lwu R28, [R28, #12] # loadN, compressed ptr, #@loadN ! Field: jdk/internal/vm/vector/VectorSupport$VectorPayload.payload (constant)
1ce decode_heap_oop R7, R28 #@decodeHeapOop
1d2 addi R7, R7, #16 # ptr, #@addP_reg_imm
1d4 loadV V2, [R7] # vector (rvv)
1dc vand_immI V1, V1, #7
1e4 spill [sp, #48] -> R7 # spill size = 32
1e6 # castII of R7, #@castII
1e6 vasrB V3, V2, V1
1fa spill [sp, #96] -> R29 # spill size = 32
1fc bgeu R7, R29, B101 #@cmpU_branch P=0.000001 C=-1.000000
```
```
--------------------------------------------------------------------------------
** Rejected vector op (RShiftVB,byte,32) because architecture does not support variable vector shifts
** not supported: arity=2 opc=405 vlen=32 etype=byte ismask=0 is_masked_op=0
```
the reason is because Matcher::supports_vector_ variable_shifts returns false. riscv vector api now supports the vector shifts, so this should return with UseRVV.
After the fix, the test passes normally and generates the JIT Code such as:
```
1c2 loadV V1, [R7] # vector (rvv)
1ca lwu R28, [R28, #12] # loadN, compressed ptr, #@loadN ! Field: jdk/internal/vm/vector/VectorSupport$VectorPayload.payload (constant)
1ce decode_heap_oop R7, R28 #@decodeHeapOop
1d2 addi R7, R7, #16 # ptr, #@addP_reg_imm
1d4 loadV V2, [R7] # vector (rvv)
1dc vand_immI V1, V1, #7
1e4 spill [sp, #48] -> R7 # spill size = 32
1e6 # castII of R7, #@castII
1e6 vasrB V3, V2, V1
1fa spill [sp, #96] -> R29 # spill size = 32
1fc bgeu R7, R29, B101 #@cmpU_branch P=0.000001 C=-1.000000
```