RISC-V: Use load instead of trampolines

Trampolines have some issues:
- On some CPUs L1D and L1I can't contain the same cache line.
  As the address in en trampoline is just under JALR we often hit this case.
  Hence the load to the address below will first need to evict the cacheline from L1I, bring it into L1D from L2(assuming it shared), load the address.
  Then the i-fetcher need to evict the cache-line from L1D bring into L1I from L2 and then execute the JALR.
  Is is very slow.
- JAL to trampoline is slower than load and JALR.

The only case where current implementation is superior is when you have very short distances so that the JAL can do directly without the trampoline to the destination (uncommon in larger workloads).