Currently, in riscv_v.ad file, we explicitly ask for the temp v registers we need, but in corresponding macro assembler code, there is no such explicit statement about it. So there is kind of a risk here, i.e. a future patch could accidentally change the code from element_compare(a1, a2, result, cnt, tmp1, tmp2, v2, v4, v2, true, DONE, Assembler::m2); to element_compare(a1, a2, result, cnt, tmp1, tmp2, v4, v8, v4, true, DONE, Assembler::m4);, on the other hand it could fail to change corresponding code in riscv_v.ad file, i.e forget to reserve the v6-v11.
I think it helps to make all such calls (i.e. vector code that use more than one v register in one register group) explicit, i.e. in riscv_v.ad file, we pass all the temporary vector registers explicitly when calling into functions in macroAssemble functions. It will make the code more tedious, but it’s safer than before, else it’s error-prone, and the potential bugs will be random.
Other solutions could be,
https://github.com/openjdk/jdk/pull/19825#discussion_r1662360642,
or https://github.com/openjdk/jdk/pull/19825#discussion_r1662493847.