RISC-V: Reduce icache flushes

Today we need to emit tens of thousands of icache_flushes and these are very expensive. By properly using the nmethod barrier and implementing runtime's cmodx fence we can significantly reduce the need for it.
By emitting fence.i directly and use PR_RISCV_SET_ICACHE_FLUSH_CTX we make sure current hart and if context switch the other hart have a fresh instruction cache:
https://docs.kernel.org/arch/riscv/cmodx.html