Fix incorrect APX feature enabling with -XX:-UseAPX

Currently VM_Supports::supports_apx_f() returns a true value even if user explicitly pass -XX:-UseAPX runtime flag, this enables APX specific code and register set.

CPROMPT>sde64 -dmr -- java -XX:+UnlockExperimentalVMOptions -Xlog:cpu+os --version | grep apx_f
[2.393s][info][os,cpu] CPU: total 112 (initial active 112) (1 cores per cpu, 2 threads per core) family 6 model 214 stepping 0 microcode 0x5003006, cx8, cmov, fxsr, ht, mmx, 3dnowpref, sse, sse2, sse3, ssse3, sse4.1, sse4.2, popcnt, lzcnt, tsc, tscinvbit, avx, avx2, aes, erms, clmul, bmi1, bmi2, adx, avx512f, avx512dq, avx512cd, avx512bw, avx512vl, sha, fma, vzeroupper, avx512_vpopcntdq, avx512_vpclmulqdq, avx512_vaes, avx512_vnni, clflush, clflushopt, clwb, avx512_vbmi2, avx512_vbmi, serialize, rdtscp, rdpid, fsrm, gfni, avx512_bitalg, f16c, pku, ospke, cet_ibt, cet_ss, avx512_ifma, avx_ifma, apx_f
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CPROMPT>sde64 -dmr -- java -XX:+UnlockExperimentalVMOptions -Xlog:cpu+os -XX:-UseAPX --version | grep apx_f
[2.406s][info][os,cpu] CPU: total 112 (initial active 112) (1 cores per cpu, 2 threads per core) family 6 model 214 stepping 0 microcode 0x5003006, cx8, cmov, fxsr, ht, mmx, 3dnowpref, sse, sse2, sse3, ssse3, sse4.1, sse4.2, popcnt, lzcnt, tsc, tscinvbit, avx, avx2, aes, erms, clmul, bmi1, bmi2, adx, avx512f, avx512dq, avx512cd, avx512bw, avx512vl, sha, fma, vzeroupper, avx512_vpopcntdq, avx512_vpclmulqdq, avx512_vaes, avx512_vnni, clflush, clflushopt, clwb, avx512_vbmi2, avx512_vbmi, serialize, rdtscp, rdpid, fsrm, gfni, avx512_bitalg, f16c, pku, ospke, cet_ibt, cet_ss, avx512_ifma, avx_ifma, apx_f