When looking at generated assembly for some intrinsics, I noticed that we have this sequence:

ldr w11, [x25]
lsr x0, x11, #0

I believe this is compressed oops decoding.

The trailing lsr looks redundant, and could be emitted as just the mov x0, x11. This would potentially set this code up for using zero-latency movs. In some cases, when dest and src regs are the same, the encoding for mov can be skipped altogether.

There is a more generic thing we can make in AArch64 MacroAssembler to rewrite these bit manipulation instructions to mov or nops where possible (JDK-8341895). This fix is surgical and thus more easily backportable.