As per AVX512-FP16 ISA specification for VMAXPH and VMINPH, NaN and -/+0.0 need the following special handling.

"If the values being compared are both 0.0s (of either sign), the value in the second operand (source
operand) is returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to
the destination (that is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either
a NaN or a valid floating-point value, is written to the result. Suppose instead of this behavior, it is required that
the NaN source operand (from either the first or second operand) be returned. In that case, the action of VMINSH can
be emulated using a sequence of instructions, such as a comparison followed by AND, ANDN, and OR."

A similar sequence was added for float/double min/max operation by the following patch on the Panama-vector branch.

commit 0357665ebe2058b174438033acdaf25a16fd50b0
Author: Jatin Bhateja <jatin.bhateja@intel.com>
Date: Wed Mar 6 13:45:32 2019 -0800

    Float/Double min/max implementation for x86

The upcoming AVX10.2 ISA extension will lift this limitation and align Min/Max with IEEE-754 specifications.