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  1. JDK
  2. JDK-8355657

RISC-V: Improve PrintOptoAssembly output of vector-scalar instructions

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    • master
    • riscv

      Let's take instruct vaddI_vi in riscv_v.ad as an example.

      ```
      // vector-immediate add (unpredicated)

      instruct vaddI_vi(vReg dst, vReg src1, immI5 con) %{
        match(Set dst (AddVB src1 (Replicate con)));
        match(Set dst (AddVS src1 (Replicate con)));
        match(Set dst (AddVI src1 (Replicate con)));
        format %{ "vaddI_vi $dst, $src1, $con" %} <====================================
        ins_encode %{
          BasicType bt = Matcher::vector_element_basic_type(this);
          __ vsetvli_helper(bt, Matcher::vector_length(this));
          __ vadd_vi(as_VectorRegister($dst$$reg),
                     as_VectorRegister($src1$$reg),
                     $con$$constant);
        %}
        ins_pipe(pipe_slow);
      %}
      ```

      This instruct matches the B, S, and I variants.
      But we use vaddI_vi as the opcode for for these variants in PrintOptoAssembly output.
      This could be misleading as the I suffix may indicate the I variant to people.
      Consider removing the I suffix and renaming this to others like vadd_vi.

            fyang Fei Yang
            fyang Fei Yang
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              Created:
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