According to the latest RISC-V linux hardware probing syscall [1], the performance of misaligned memory accesses has been divided into two cases: `RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF` and `RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF` for scalar and vector respectively.

This aligns `AlignVector` with `RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`. That is if the misaligned vector access is fast, we set `AlignVector` to false in the hope that it will save instructions handling address alignment thus improves performance.