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Enhancement
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Resolution: Fixed
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P4
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25, 26
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b18
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riscv
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linux
| Issue | Fix Version | Assignee | Priority | Status | Resolution | Resolved In Build |
|---|---|---|---|---|---|---|
| JDK-8369245 | 25.0.2 | Dingli Zhang | P4 | Resolved | Fixed | master |
According to the latest RISC-V linux hardware probing syscall [1], the performance of misaligned memory accesses has been divided into two cases: `RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF` and `RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF` for scalar and vector respectively.
This aligns `AlignVector` with `RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`. That is if the misaligned vector access is fast, we set `AlignVector` to false in the hope that it will save instructions handling address alignment thus improves performance.
This aligns `AlignVector` with `RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`. That is if the misaligned vector access is fast, we set `AlignVector` to false in the hope that it will save instructions handling address alignment thus improves performance.
- backported by
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JDK-8369245 RISC-V: Detect support for misaligned vector access via hwprobe
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- Resolved
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- relates to
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JDK-8368722 RISC-V: Several vector load/store tests fail due to lack of support for misaligned vector access
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- Open
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- links to
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Commit(master)
openjdk/jdk25u/66de4b41
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Commit(master)
openjdk/jdk/538a722c
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Review(master)
openjdk/jdk25u/252
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Review(master)
openjdk/jdk/27512
(1 links to)