x86 backend support for add/mul reduction operations for Float16

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    • Type: Enhancement
    • Resolution: Unresolved
    • Priority: P4
    • tbd
    • Affects Version/s: 26
    • Component/s: hotspot
    • x86_64
    • generic

      Given that the auto-vectorized generated vector reduction operations are strictly ordered, there may not be any tangible performance uplift, while the vector API is relaxed in terms of precision requirements, which allows application of D&C to build a reduction tree.

            Assignee:
            Jatin Bhateja
            Reporter:
            Jatin Bhateja
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              Created:
              Updated: