The C2 output stage uses fixed latencies to drive scheduling of instructions which lie in a common instruction bundle. Latencies are used to associate instructions with pipeline elements in the associated processor model and test for pipeline access clashes under some given instruction ordering. Latencies that exceed the depth of the pipeline do not make sense. However, various arches currently employ such latencies.

Before simply tuning down these latencies so they are in range it would be better to assess the value of the pipeline model to decide whether the use of latencies still makes any sense with current, mostly OOO architectures. If the pipeline model is still useful then the latencies should be adjusted into range while ensuring that any resulting changes to schedule order do not damage performance. If the pipeline model is not useful then it can be removed and replaced with a simpler scheduling strategy.