Master thesis work explored a GC-agnostic write barrier implementation for G1, Z, Serial, and Parallel collectors to enable AOT compilation in Leyden. In the implementation, the write barriers for Serial and Parallel were also modified to be expanded late by C2. Evaluations showed a negligible to small effect on performance.

Implementation: https://github.com/sigrvn/jdk/tree/gc-agnostic-store-barriers/
Master thesis work: https://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-565630

Another implementation, not relying on UB, was also carried out as part of the two-prone approach to write barriers.
Implementation: https://github.com/sigrvn/jdk/tree/gcafmasb
Master thesis work: https://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-569546

While load barriers are not relevant to Serial and Parallel, prototypes may still provide some information.
Implementation: https://github.com/Arraying/jdk-gcalb
Master thesis work: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-368017