This issue is based on
- https://github.com/corretto/corretto-jdk/issues/136
- https://product.hubspot.com/blog/its-never-a-hardware-bug-until-it-is

When GenZGC updates barriers it invalidates the instruction cache.
Neoverse-N1 (r3p0, r3p1, and r4p0) has erratum 1542419 "The core might fetch a stale instruction from memory which violates the ordering of instruction fetches" which is fixed in r4p1.

Neoverse-N1 implementation mitigates the erratum with a workaround:
- Disable coherent icache.
- Trap IC IVAU instructions.
- Execute the TLB inner-shareable invalidation and DSB operations.

This workaround cause significant performance degradation of GenZGC, see the links above.

Arm Neoverse N1 (MP050) Software Developer Errata Notice version 29.0 suggests:

"Since one TLB inner-shareable invalidation is enough to avoid this erratum, the number of injected TLB invalidations should be minimized in the trap handler to mitigate the performance impact due to this workaround."

The performance degradation scales linearly for the average number of barriers per nmethod.

We patch only armed nmethods. So it should be safe to invalidate icache with the workaround once we have finished all patching in an nmethod.