For certain constant multipliers like the following

"6", "7", "10", "11", "13",
"15", "17", "19", "21", "25",
"27", "37", "41", "45", "73", "81"

Currently, we emit an IMUL instruction with a fixed 3-cycle latency on
Both x86-based CPUs.

The multiplications can be optimized using two LEA instructions as
mentioned by Matt Godbolt in the Advent of Compiler Optimization Series 2025

https://www.linkedin.com/posts/godbolt_aoco2025-activity-7402317971286900737-9s4l?utm_source=share&utm_medium=member_desktop&rcm=ACoAAADvcegBbPEpulW0l3dA_RF_nXL-wpD6T2s