Inconsistent register encoding for IMUL with immediate operand on APX target

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    • Type: Bug
    • Resolution: Cannot Reproduce
    • Priority: P4
    • None
    • Affects Version/s: 27
    • Component/s: hotspot
    • x86_64
    • generic

      The following test point shows different register encoding for IMULL with imm operands in opto and jit assembly.

      Opto:
      025 imulq R17, [R16 + #120 (8-bit)], #13104 # long
      JIT:
        0x00007d44a7e80f27: imul $0x3330,0x78(%rax),%ecx

      imul is a MAP0/1 instruction which should emit REX2 encoding with EGPR operands.

      Following four selection patterns needs to be analysed as they are missing UseAPX predication.

      instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
      %{
        match(Set dst (MulI src imm));
        effect(KILL cr, TEMP_DEF dst);

      instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
      %{
        match(Set dst (MulI (LoadI src) imm));
        effect(KILL cr, TEMP dst);

      instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
      %{
        match(Set dst (MulL src imm));
        effect(KILL cr, TEMP_DEF dst);

      instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
      %{
        match(Set dst (MulL (LoadL src) imm));
        effect(KILL cr, TEMP dst);

            Assignee:
            Jatin Bhateja
            Reporter:
            Jatin Bhateja
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              Created:
              Updated:
              Resolved: