Currently, the masked versions of the following 8 Float16 operations are not supported.
But we return true in `Matcher::match_rule_supported_vector_masked` for these operations
on RISC-V platforms with Zvfh. We need to explicitly disable them on this CPU platform
to make it clear.

 Op_AddVHF:
 Op_SubVHF:
 Op_MulVHF:
 Op_DivVHF:
 Op_MaxVHF:
 Op_MinVHF:
 Op_SqrtVHF:
 Op_FmaVHF:

When the support for Float16 vector classes is added in VectorAPI and the masked
Float16 IR can be generated, these masked operations will be enabled and relevant
backend support added.