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Type:
Bug
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Resolution: Fixed
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Priority:
P4
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Affects Version/s: 27
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Component/s: hotspot
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b04
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riscv
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linux
| Issue | Fix Version | Assignee | Priority | Status | Resolution | Resolved In Build |
|---|---|---|---|---|---|---|
| JDK-8374938 | 25.0.3 | Dingli Zhang | P4 | Resolved | Fixed | master |
Currently, the masked versions of the following 8 Float16 operations are not supported.
But we return true in `Matcher::match_rule_supported_vector_masked` for these operations
on RISC-V platforms with Zvfh. We need to explicitly disable them on this CPU platform
to make it clear.
Op_AddVHF:
Op_SubVHF:
Op_MulVHF:
Op_DivVHF:
Op_MaxVHF:
Op_MinVHF:
Op_SqrtVHF:
Op_FmaVHF:
When the support for Float16 vector classes is added in VectorAPI and the masked
Float16 IR can be generated, these masked operations will be enabled and relevant
backend support added.
But we return true in `Matcher::match_rule_supported_vector_masked` for these operations
on RISC-V platforms with Zvfh. We need to explicitly disable them on this CPU platform
to make it clear.
Op_AddVHF:
Op_SubVHF:
Op_MulVHF:
Op_DivVHF:
Op_MaxVHF:
Op_MinVHF:
Op_SqrtVHF:
Op_FmaVHF:
When the support for Float16 vector classes is added in VectorAPI and the masked
Float16 IR can be generated, these masked operations will be enabled and relevant
backend support added.
- backported by
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JDK-8374938 RISC-V: Several masked float16 vector operations are not supported
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- Resolved
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- links to
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Commit(master)
openjdk/jdk25u-dev/fd0436b5
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Commit(master)
openjdk/jdk/df5b49e6
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Review(master)
openjdk/jdk25u-dev/133
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Review(master)
openjdk/jdk/29035