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Type:
Enhancement
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Resolution: Unresolved
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Priority:
P4
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Affects Version/s: 27
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Component/s: hotspot
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riscv
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linux
On behalf of Zhenjun Feng <fengzhenjun.fzj@alibaba-inc.com>
The RISC-V addiw instruction includes built-in sign extension. When the 32-bit immediate value is 0, no sign extension is needed. The current JIT assembler generates a redundant zext.w instruction.
The RISC-V addiw instruction includes built-in sign extension. When the 32-bit immediate value is 0, no sign extension is needed. The current JIT assembler generates a redundant zext.w instruction.