AArch64: Add fusion optimization support for specific SVE instructions

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    • Type: Enhancement
    • Resolution: Unresolved
    • Priority: P4
    • tbd
    • Affects Version/s: 27
    • Component/s: hotspot
    • aarch64
    • generic

      A lots of SVE instructions require the dst register to be the same with first source register to save encodings. For example `add z18.b, p0/m, z18.b, z17.b`. In order to meet this requirement, and save the value of the source register, we have to insert a `mov` instruction before this kind of instructions. For example:
      ```
      mov z16.b, z18.b // save the value of z18
      add z16.b, p0/m, z16.b, z17.b
      ```
      This `mov` may be inserted manually or via Register allocator.

      The `mov` instruction can be optimized as an SVE `movprfx` instruction for better performance. For the above example, it becomes:
      ```
      movprfx z16, z18
      add z16.b, p0/m, z16.b, z17.b
      ```
      The above two instructions will be fused as if one instruction in hardware, like:
      ```
      add z16.b, p0/m, z18.b, z17.b
      ```

            Assignee:
            Eric Fang
            Reporter:
            Eric Fang
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              Created:
              Updated: