JDK-8196064 added support for merging 4- and 8-byte scalar load/store operations into load/store pairs. The AArch64 platform also supports SIMD load/store pairs for SIMD&FP registers. For example, the stp instruction can combine two adjacent 128-bit stores into a single store-pair operation.
Given assembly like:
str q16, [x14, #32]
str q16, [x14, #48]
this can be merged into:
stp q16, q16, [x14, #32]