riscv: Fix callee-saved float register definitions: should be SOE

XMLWordPrintable

    • Type: Bug
    • Resolution: Fixed
    • Priority: P4
    • repo-riscv-port
    • Affects Version/s: repo-riscv-port
    • Component/s: hotspot
    • None
    • riscv
    • linux

      There are unnecessary float register spills before leaf calls and it seems that callee-saved float registers' definitions should be SOE so the register allocator may firstly use these SOE registers as allocation candidates to prevent spills before leaf calls. I have looked through F8-F9, F18-F27 usages and found they are not used in any stub so it could be safe. Tested all cases.

      This fix is nearly the same as JDK-8253048 on the aarch64 platform and receives an identical result.

            Assignee:
            Xiaolin Zheng
            Reporter:
            Xiaolin Zheng
            Votes:
            0 Vote for this issue
            Watchers:
            1 Start watching this issue

              Created:
              Updated:
              Resolved: