riscv: RVB: Add bitwise rotation instructions

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    • Type: Enhancement
    • Resolution: Fixed
    • Priority: P4
    • repo-riscv-port
    • Affects Version/s: repo-riscv-port
    • Component/s: hotspot
    • None

      This issue implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw.

      This issue also add zext/sext C2 instructions that were missed in JDK-8279213

            Assignee:
            Feilong Jiang
            Reporter:
            Feilong Jiang
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              Created:
              Updated:
              Resolved: