Currently G1 (and Shenandoah) implicitly uses x13 on riscv in oop_store_at.
This out of the blue register fixed for x86 inJDK-8283186. This would be fixed in the same way on riscv by passing the temporary register explicitly so it is part of the GC API.
This out of the blue register fixed for x86 in
- relates to
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JDK-8283186 Explicitly pass a third temp register to MacroAssembler::store_heap_oop
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- Resolved
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