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  1. JDK
  2. JDK-8293290

RISC-V: Explicitly pass a third temp register to MacroAssembler::store_heap_oop

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    • Enhancement
    • Resolution: Fixed
    • P4
    • 20
    • 20
    • hotspot
    • None
    • gc
    • b14
    • riscv
    • linux

    Description

      Currently G1 (and Shenandoah) implicitly uses x13 on riscv in oop_store_at.

      This out of the blue register fixed for x86 in JDK-8283186. This would be fixed in the same way on riscv by passing the temporary register explicitly so it is part of the GC API.

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              fyang Fei Yang
              fyang Fei Yang
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                Created:
                Updated:
                Resolved: