Currently G1 (and Shenandoah) create a temporary register out of thin air in G1BarrierSetAssembler::oop_store_at for x86
It is much less surprising to pass that third temporary in MacroAssembler::store_heap_oop (like on other platforms)
It is much less surprising to pass that third temporary in MacroAssembler::store_heap_oop (like on other platforms)
- relates to
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JDK-8292868 Explicitly pass a third temp register to MacroAssembler::store_heap_oop for aarch64
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- Resolved
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- Resolved
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