RISC-V: Remove implicit noreg temp register arguments in MacroAssembler

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    • Type: Enhancement
    • Resolution: Fixed
    • Priority: P4
    • 20
    • Affects Version/s: 20
    • Component/s: hotspot
    • None
    • b21
    • riscv
    • linux

      Remove implicit `= noreg` temporary register arguments for the three methods that still have them.
        * `load_heap_oop`
        * `store_heap_oop`
        * `load_heap_oop_not_null`

      Only `load_heap_oop` is used with the implicit `= noreg` arguments.
      After JDK-8293769, the GCs only use explicitly passed in registers. This will also be the case for generational ZGC.
      Where it currently requires `load_heap_oop` to provide a second temporary register.

            Assignee:
            Fei Yang
            Reporter:
            Fei Yang
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              Created:
              Updated:
              Resolved: