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Enhancement
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Resolution: Fixed
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P4
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21, 22
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b25
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riscv
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linux
| Issue | Fix Version | Assignee | Priority | Status | Resolution | Resolved In Build |
|---|---|---|---|---|---|---|
| JDK-8320722 | 21.0.2 | Gui Cao | P4 | Resolved | Fixed | b09 |
This is inspired by https://bugs.openjdk.org/browse/JDK-8316880.
MacroAssembler::lightweight_lock/unlock is non-trivial on linux-riscv64 platform. Passing t0(aka x5) as temporary register to these two assember functions can also be error prone. As a reserved scratch register, t0 is implicitly clobberred by various assembler functions. This fixes the issue by finding and passing a different register, which is similar with https://bugs.openjdk.org/browse/JDK-8316880.
MacroAssembler::lightweight_lock/unlock is non-trivial on linux-riscv64 platform. Passing t0(aka x5) as temporary register to these two assember functions can also be error prone. As a reserved scratch register, t0 is implicitly clobberred by various assembler functions. This fixes the issue by finding and passing a different register, which is similar with https://bugs.openjdk.org/browse/JDK-8316880.
- backported by
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JDK-8320722 RISC-V: Avoid passing t0 as temp register to MacroAssembler::lightweight_lock/unlock
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- Resolved
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