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Enhancement
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Resolution: Unresolved
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P4
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25
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riscv
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linux
RISC-V base ISA (RV64GCV) does not support conditional move, so we set `ConditionalMoveLimit` to 0 for this CPU platform. For performance reasons, we should reconsider this parameter when adding conditional move with Zicond extension.
- relates to
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JDK-8346787 Fix two C2 IR matching tests for RISC-V
- Resolved
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JDK-8344306 RISC-V: Add zicond
- Resolved