Current c1_Defs_riscv.hpp limits allocatable registers to caller-saved ones (like it used to be on aarch64):

```
  pd_nof_caller_save_cpu_regs_frame_map = 13, // number of registers killed by calls
  pd_nof_caller_save_fpu_regs_frame_map = 32, // number of float registers killed by calls

  pd_first_callee_saved_reg = pd_nof_caller_save_cpu_regs_frame_map,
  pd_last_callee_saved_reg = 21,

  pd_last_allocatable_cpu_reg = pd_nof_caller_save_cpu_regs_frame_map - 1,
```

Aditional registers can be enabled similar to aarch64 (JDK-8347917).