Currently G1 (and Shenandoah) implicitly uses r3 on aarch64 in store_at.
This out of the blue register fixed for x86 inJDK-8283186. This would be fixed in the same way on aarch64 by passing the temporary register explicitly so it is part of the GC api.
This out of the blue register fixed for x86 in
- relates to
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JDK-8338881 GenShen: Use explicit third temp register for post barrier
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- Resolved
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JDK-8283186 Explicitly pass a third temp register to MacroAssembler::store_heap_oop
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- Resolved
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